This invention relates to a method for reading semiconductor memories and in particular to an improved method for reading metal dual insulator semiconductor memory arrays in which each memory cell is a capacitor which exhibits hysteresis under a varying applied voltage.
Semiconductor memories have been in existence for many years. They generally comprise a plurality of semiconductor elements organized into a regular cellular array which is fabricated on a single chip. Each cell is capable of storing one binary digit or one bit. Each cell may typically be a complex structure, often including three or more terminals to effect reading and writing of the memory.
While prior art semiconductor memories have been useful, they have generally consisted of relatively complex configurations. This increases the cost of fabrication and the size of each cell.
Dual dielectric capacitor memories have been suggested to decrease both cost of fabrication and size. Generally however they have not succeeded in providing practical structures and methods for selectively reading and writing at high speeds.
Dual dielectric capacitor memories are desirable however because they have the potential of providing extremely high densities in a cross-point addressing lattice and require zero standby power and negligible refresh power.
At present, the generally preferred MIS capacitor memories most often use a four layer metal-nitride-oxide-silicon (MNOS) structure (a dual insulator, MIS capacitor).
As in any MIS structure, the MNOS capacitor has a capacitance which is voltage dependent. Unlike devices having a single dielectric layer, such as MOS capacitors, however, the capacitance versus voltage curve of the MNOS device exhibits hysteresis which arises from trapping of charge near the interface between the two dielectric layers. This trapped charge, whose magnitude depends on the duration and magnitude of applied voltage, effectively provides a bias voltage which corresponds to a shift of the voltage-capacitance relationship along the voltage axis corresponding to a change in the "flat band" voltage.
The charge storage in an MNOS capacitor arises from a net imbalance in the currents which flow in the nitride and oxide layers respectively. Current flow in the oxide is primarily tunneling and current flow in the nitride is primarily Poole-Frenkel conduction. The tunneling mechanism in the oxide layer and the Poole-Frenkel conduction mechanism in the nitride layer are extremely non-linear with field. Thus small changes in thickness and dielectric fabrication conditions can lead to a higher current in a selected one of the two dielectrics. In one condition, if the oxide current exceeds the nitride current, then a positive pulse at the metal terminal causes more electrons to enter the oxide than leave the nitride and a net negative charge can build up at the nitride-oxide interface. A negative pulse at the metal terminal can leave a net positive charge at the interface. Conversely, if the nitride current exceeds the oxide current, a positive pulse produces a positive change in charge and a negative pulse results in a negative change in stored charge. The two modes described above are referred to as the forward (or normal) mode (oxide current greater than nitride current) and the reverse (or complementary) mode (oxide current less than nitride current). A binary "1" or "0" can be associated with any two arbitrarily selected storage states.
In practice, the straight-forward prior art approach to writing by applying different potential polarities and thereby creating different charge storage states is of limited usefulness. For example, operating in the forward mode, the speed with which the quantity of stored charge can be changed in the positive direction at the nitride-oxide interface in response to a negative pulse is limited to about a few milliseconds in a typical N-type MNOS capacitor cell. In contrast, the time required to build up stored charge in the negative direction in the device, in a practical system, can be as low as one microsecond or less with a thirty volt pulse. This striking difference in charging times is due to the creation of a small series capacitance in the semiconductor substrate as a negative voltage is applied to an MNOS capacitor formed on N-type silicon. A capacitor is formed by the depletion of the silicon nearest the oxide of electrons under the influence of the field which repels electrons from the metal. This depletion effectively places a high impedance (low capacitance) in series with the dual dielectric capacitance (the nitride and oxide layers). Thus, the prior art approach to writing is limited because this series depletion capacitance soaks up most of the voltage applied across the MNOS device, leaving relatively little voltage available across the nitride-oxide layers to provide the currents needed for writing in the negative direction. (A positive pulse applied to a P-type substrate produces a similar effect.) After a sufficiently long time (typically milliseconds) an inversion layer will form causing the substrate capacitance to return to its high value and permitting dielectric currents to flow. The asymmetry in writing speeds for two selected storage states is a significant deterrent to the use of capacitors in read-write memories.
Reading or determining the state of a capacitor memory cell has, in the past, been implemented by measuring the absolute capacitance of the cell and correlating it to the capacitance-voltage hysteresis loop. The read techniques vary but are generally characterized by applying a small AC signal across the capacitor cell and measuring the resulting current. After adjusting the measurements for background parasitic and coupling capacitances, the resulting measurement of current provides a measure of the capacitance and hence the state of the cell.
Unfortunately, measuring or "reading" the absolute capacitance of a cell, is, in practice, extremely difficult because the parasitic, coupling and other capacitances inherent in a very large array tend to swamp the relatively small cell capacitance and thus provide a very low signal to noise ratio.
Copending application Ser. No. 737,165 noted above of which this application is a continuation-in-part discloses and claims a capacitor memory array and methods for reading and writing in the array which substantially overcome the basic problems which existed in the past in connection with capacitor arrays. Even though the method of reading the capacitor described in that copending application is a significant advance over the prior art, still further improvements are possible.
It is therefore an object of this invention to provide an improved method for reading a capacitor memory array which provides, without additional cost in either complexity or equipment, a substantially improved output signal in the read mode. Other objects of the invention are to provide a method for reading which does not depend on the absolute value of capacitance of the individual cell and which does not disturb the information stored in unselected cells which may share the same word and/or digit lines associated with the selected cell.